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Silicon Labs /Series1 /EFM32TG11B /EFM32TG11B120F128GM32 /SMU /PPUPATD0

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Interpret as PPUPATD0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ACMP0)ACMP0 0 (ACMP1)ACMP1 0 (ADC0)ADC0 0 (CAN0)CAN0 0 (CMU)CMU 0 (CRYOTIMER)CRYOTIMER 0 (CRYPTO0)CRYPTO0 0 (CSEN)CSEN 0 (VDAC0)VDAC0 0 (PRS)PRS 0 (EMU)EMU 0 (GPCRC)GPCRC 0 (GPIO)GPIO 0 (I2C0)I2C0 0 (I2C1)I2C1 0 (MSC)MSC 0 (LDMA)LDMA 0 (LESENSE)LESENSE 0 (LETIMER0)LETIMER0 0 (LEUART0)LEUART0 0 (PCNT0)PCNT0 0 (RMU)RMU 0 (RTCC)RTCC 0 (SMU)SMU 0 (TIMER0)TIMER0 0 (TIMER1)TIMER1 0 (TRNG0)TRNG0 0 (UART0)UART0 0 (USART0)USART0 0 (USART1)USART1 0 (USART2)USART2

Description

PPU Privilege Access Type Descriptor 0

Fields

ACMP0

Analog Comparator 0 access control bit
ACMP1

Analog Comparator 1 access control bit
ADC0

Analog to Digital Converter 0 access control bit
CAN0

CAN 0 access control bit
CMU

Clock Management Unit access control bit
CRYOTIMER

CRYOTIMER access control bit
CRYPTO0

Advanced Encryption Standard Accelerator access control bit
CSEN

Capacitive touch sense module access control bit
VDAC0

Digital to Analog Converter 0 access control bit
PRS

Peripheral Reflex System access control bit
EMU

Energy Management Unit access control bit
GPCRC

General Purpose CRC access control bit
GPIO

General purpose Input/Output access control bit
I2C0

I2C 0 access control bit
I2C1

I2C 1 access control bit
MSC

Memory System Controller access control bit
LDMA

Linked Direct Memory Access Controller access control bit
LESENSE

Low Energy Sensor Interface access control bit
LETIMER0

Low Energy Timer 0 access control bit
LEUART0

Low Energy UART 0 access control bit
PCNT0

Pulse Counter 0 access control bit
RMU

Reset Management Unit access control bit
RTCC

Real-Time Counter and Calendar access control bit
SMU

Security Management Unit access control bit
TIMER0

Timer 0 access control bit
TIMER1

Timer 1 access control bit
TRNG0

True Random Number Generator 0 access control bit
UART0

Universal Asynchronous Receiver/Transmitter 0 access control bit
USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit
USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit
USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data